1. Field of the Invention
The present invention relates to optimizing the electrical characteristics of an integrated circuit (IC) by modifying the physical layout of the IC. More specifically, the present invention determines when regions of the IC, related to various standard cells, in the IC design are under-utilized. The present invention then includes appropriate electrical components in such under-utilized areas to increase electrical performance, such as stabilizing the power supplied to various logic areas of the IC, such as super blocks or macros.
2. Description of Related Art
As integrated circuit technology becomes more advanced, geometries (line width, cross-sectional area and spacing) become smaller causing parasitics (e.g. electrical noise) to become larger. Further, today""s advanced technologies are driving voltages to become lower and speeds to become faster. This causes a greater need for on-chip bypass capacitance in order to stabilize the power supply to the logic components of the chip.
Additionally, there are situations with deep sub-micron designs when it is a problem to ensure a stable power and ground supply in areas of the floorplan such as high-speed logic areas, high density logic areas and areas which are substantial distances for a stable power source.
Typically, circuit designers provide gate capacitors to stabilize the power supplies, but this capacitor region is usually separated from the affected logic. That is, the gate capacitors of the prior art are remote from the logic which is most affected by the electrical parasitics. Due to this separation, the prior art gate capacitors can only minimally improve the electrical power characteristics of the logic they were intended to support.
Therefore, it can be seen that a need exists for a technique that can efficiently and automatically place gate capacitors, or other electrical components near the logic that requires a stable power supply during the physical layout of an integrated circuit.
When performing the physical layout of an integrated circuit, there are times when various conditions leave an under-utilized space relative to the amount of logic to be placed in a specific area of the chip.
In contrast to the prior art, the present invention provides a system and method for placing gate capacitors, or other performance enhancing electrical components, in an under-utilized standard cell region. Further, it is contemplated by the present invention to intentionally under utilize various functional blocks in order to create areas that can be filled with cells containing gate capacitors.
Broadly, the present invention is a layout design tool that allows the designer to automatically intersperse capacitor filler cells among standard cell logic. The present invention includes creating a region, allocated to the particular standard cell, which has (either by intention or situation) low utilization. The standard cells may or may not be associated with surrounding logic. The place and route filler cells are redefined to include gate capacitors using abutment rules compatible with the standard cells. This allows the place and route tool, or the like, to locate gate capacitors in the xe2x80x9clegalxe2x80x9d placement locations not used by standard cells within the under-utilized region. The standard cell region being used for this purpose shares the power and ground supply with the power sensitive areas of the logic. The present invention provides a stable power supply throughout the die with improved efficiency due to block abutments and/or timing constraints between areas using standard cell glue logic and the reduction in time required for implementation of power/ground bypass capacitors.
Therefore, in accordance with the previous summary, objects, features and advantages of the present invention will become apparent to one skilled in the art from the subsequent description and the appended claims taken in conjunction with the accompanying drawings.